This invention relates to a self-aligned via between interconnect layers in an integrated circuit and to a process for forming such a via.
In the fabrication of semiconductor memory devices and other types of integrated circuits, two or more conductive layers known as interconnect layers are commonly deposited. These interconnect layers are separated, for example, by one or more dielectric layers. Various methods may be used to make electrical connections between these interconnect layers. One such method includes (a) forming a first dielectric layer, (b) depositing a first interconnect layer (xe2x80x9cPoly 1xe2x80x9d), (c) masking and etching Poly 1 to form conductive leads, (d) depositing a second dielectric layer, (e) masking and etching the second dielectric layer to form a xe2x80x9cviaxe2x80x9d (a small opening) completely through the second dielectric layer to a Poly 1 conductive lead, and (f) depositing a second interconnect layer (xe2x80x9cPoly 2xe2x80x9d) in and over the via so that electrical contact between Poly 1 and Poly 2 is made through a xe2x80x9cplugxe2x80x9d of conductive material which fills the via. One of the difficulties in using this method is that it is necessary to compensate for possible misalignment of the via mask. For example, a misalignment of the via mask may shift the via sideways so that the via is not formed entirely over the Poly 1 conductor. Instead, the via may overlap onto the first dielectric layer alongside a Poly 1 conductor, exposing the first dielectric layer during the via etch step, and allowing a groove to be etched in the first dielectric layer during the via etch step. The groove may cause microcracking or thinning of the Poly 2 conductor when it is deposited in and over the via to contact the Poly 1 conductor. This can be avoided by widening the Poly 1 conductor at the via location so that even a misaligned via will not overlap onto the first dielectric layer. However, locally widening the Poly 1 conductor conflicts with the goal of reducing the size of the integrated circuit and increasing its packing density.
It is desirable to decrease the memory cell size in fabricating semiconductor memory devices such as random access memory chips, in order to increase the packing density. A major factor limiting further increases in packing density is the alignment tolerance of the via mask used in forming a via between Poly 1 and Poly 2.
In accordance with the present invention, a process is provided for forming a self-aligned via between interconnect layers on an integrated circuit chip. This self-aligned feature permits a less precise masking alignment to be used in forming such a via, without the disadvantage of locally widening the Poly 1 conductor at the via location as in the prior art process described above. In the present invention, the smaller linewidth of the Poly 1 conductor at the via location makes it possible to fabricate an integrated circuit with greater packing density, reduced die size, and improved yield.
In one embodiment, the process of the present invention includes (a) depositing a first conductive layer overlying one surface of a semiconductor substrate, (b) forming a first dielectric layer directly upon the first conductive layer, (c) masking and etching the first dielectric layer to form a via, (d) forming a conductive plug within the via, (e) masking and etching the conductive plug, the first dielectric layer, and the first conductive layer to form an interconnect structure, (f) depositing a second dielectric layer overlying the substrate and the interconnect structure, (g) etching the second dielectric layer to expose the upper surface of the conductive plug, and (h) forming a second interconnect layer overlying the second dielectric layer so that an electrical connection is formed between the first and second interconnect layers. The resulting structure will have a conductive plug formed within the self-aligned via, with one edge of the conductive plug normally being aligned with one edge of the first interconnect layer, and the other edge of the conductive plug either lying above the first interconnect layer or aligned with the other edge of the first interconnect layer. If the via mask is perfectly aligned, both edges of the conductive plug will be aligned with the edges of the first interconnect layer.